| Step 1: Prepare an Requirement Specification | | | | power-target's of the Chip . |
| | | | |
| Step 2: Create an Micro-Architecture | | | | Step 10: The next step is to perform the |
| Document. | | | | Routing., at first the Global routing and |
| | | | Detailed routing, meeting the DRC(Design Rule |
| Step 3: RTL Design & Development of IP's | | | | Check) requirement as per the fabrication |
| | | | requirement. |
| Step 4: Functional verification all the IP's | | | | |
| Check whether the RTL is free from Linting | | | | Step 11: After performing Routing then the |
| Errors/Analyze whether the RTL is Synthesis | | | | routed Verilog netlist, standard-cells LEF |
| friendly. | | | | DEF file is taken to the Extraction tool (to |
| | | | extract the parasitics(RLC) values of the |
| Step 4a: Perform Cycle-based | | | | chip in the SPEF format(Standard parasitics |
| verification(Functional) to verify the | | | | Exchange Format), and the SPEF file is |
| protocol behaviour of the RTL | | | | generated. |
| | | | |
| Step 4b: Perform Property Checking , to | | | | Step 12: Check whether the Design is meeting |
| verify the RTL implementation and the | | | | the requirements (Functional/Timing/Area |
| specification understanding is matching. | | | | Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after |
| | | | Placement and Routing step. |
| Step 5: Prepare the Design Constraints file | | | | |
| (clock definitions(frequency/uncertainity | | | | Step 12a: Perform the Routed Netlist-level |
| jitter),I/O delay definitions, Output pad | | | | Power Analysis, to know whether the design |
| load definition, Design False | | | | has met the power targets. |
| Multicycle-paths) to perform Synthesis, | | | | |
| usually called as an SDC | | | | Step 12b: Perform Gate-level Simulation with |
| synopsys_constraints, specific to synopsys | | | | the routed Netlist to check whether the |
| synthesis Tool (design-compiler) | | | | design is meeting the functional requirement |
| | | | . |
| Step 6: To Perform Synthesis for the IP, the | | | | |
| inputs to the tool are (library file(for | | | | Step 12c: Perform Formal-verification between |
| which synthesis needs to be targeted for, | | | | RTL vs routed Netlist to confirm that the |
| which has the functional/timing information | | | | place & route Tool has not altered the |
| available for the standard-cell library and | | | | functionality. |
| the wire-load models for the wires based on | | | | |
| the fanout length of the connectivity), RTL | | | | Step 12d: Perform STA(Static Timing Analysis) |
| files and the Design Constraint files, So | | | | with the SPEF file and routed netlist file, |
| that the Synthesis tool can perform the | | | | to check whether the Design is meeting the |
| synthesis of the RTL files and map and | | | | timing-requirements. |
| optimize to meet the design-constraints | | | | |
| requirements. After performing synthesis, as | | | | Step 12e: Perform Scan-Tracing , in the DFT |
| a part of the synthesis flow, need to build | | | | tool, to check whether the scan-chain is |
| scan-chain connectivity based on the | | | | built based on the DFT requirement, Peform |
| DFT(Design for Test) requirement, the | | | | the Fault-coverage with the DFT tool and |
| synthesis tool (Test-compiler), builds the | | | | Generate the ATPG test-vectors. |
| scan-chain. | | | | |
| | | | Step 12f: Convert the ATPG test-vector to a |
| 7: Check whether the Design is meeting the | | | | tester understandable format(WGL) |
| requirements (Functional/Timing/Area/Power | | | | |
| DFT) after synthesis. | | | | Step 12g: Perform DRC(Design Rule Check) |
| | | | verfication called as Physical-verification, |
| Step 7a: Perform the Netlist-level Power | | | | to confirm that the design is meeting the |
| Analysis, to know whether the design is | | | | Fabrication requirements. |
| meeting the power targets. | | | | |
| | | | Step 12h: Perform LVS(layout vs Spice) check, |
| Step 7b: Perform Gate-level Simulation with | | | | a part of the verification which takes a |
| the Synthesized Netlist to check whether the | | | | routed netlist converts to spice (call it |
| design is meeting the functional | | | | SPICE-R) and convert the Synthesized |
| requirements. | | | | netlist(call it SPICE-S) and compare that the |
| | | | two are matching. |
| Step 7c: Perform Formal-verification between | | | | |
| RTL vs Synthesized Netlist to confirm that | | | | Step 12i : Perform the ERC(Electrical Rule |
| the synthesis Tool has not altered the | | | | Checking) check, to know that the design is |
| functionality. | | | | meeting the ERC requirement. |
| | | | |
| Step 7d: Perform STA(Static Timing Analysis) | | | | Step 12j: Perform the ESD Check, so that the |
| with the SDF(Standard Delay Format) file and | | | | proper back-to-back diodes are placed and |
| synthesized netlist file, to check whether | | | | proper guarding is there in case if we have |
| the Design is meeting the | | | | both analog and digital portions in our Chip. |
| timing-requirements. | | | | We have seperate Power and Grounds for both |
| | | | Digital and Analog Portions, to reduce the |
| Step 7e: Perform Scan-Tracing , in the DFT | | | | Substrate-noise. |
| tool, to check whether the scan-chain is | | | | |
| built based on the DFT requirement. | | | | Step 12k: Perform seperate STA(Static Timing |
| | | | Analysis) , to verify that the |
| Step 8: Once the synthesis is performed the | | | | Signal-integrity of our Chip. To perform this |
| synthesized netlist file(VHDL/Verilog format) | | | | to the STA tool, the routed netlist and SPEF |
| and the SDC (constraints file) is passed as | | | | file(parasitics including coupling |
| input files to the Placement and Routing Tool | | | | capacitances values), are fed to the tool. |
| to perform the back-end Actitivities. | | | | This check is important as the |
| | | | signal-integrity effect can cause cross-talk |
| Step 9: The next step is the Floor-planning, | | | | delay and cross-talk noise effects, and |
| which means placing the IP's based on the | | | | hinder in the functionality/timing aspects of |
| connectivity,placing the memories, Create the | | | | the design. |
| Pad-ring, placing the Pads(Signal/power | | | | |
| transfer-cells(to switch voltage domains | | | | Step 12l: Perform IR Drop analysis, that the |
| Corner pads(proper accessibility for Package | | | | Power-grid is so robust enough to with-stand |
| routing), meeting the SSN | | | | the static and dynamic power-drops with in |
| requirements(Simultaneous Switching Noise) | | | | the design and the IR-drop is with-in the |
| that when the high-speed bus is switching | | | | target limits. |
| that it doesn't create any noise related | | | | |
| acitivities, creating an optimised floorplan, | | | | Step 13: Once the routed design is verified |
| where the design meets the utilization | | | | for the design constraints, then now the next |
| targets of the chip. | | | | step is chip-finishing activities (like |
| | | | metal-slotting, placing de-coupling caps). |
| Step 9a : Release the floor-planned | | | | |
| information to the package team, to perform | | | | Step 14: Now the Chip Design is ready to go |
| the package feasibility analysis for the | | | | to the Fabrication unit, release files which |
| pad-ring . | | | | the fab can understand, GDS file. |
| | | | |
| Step 9b: To the placement tool, rows are cut, | | | | Step 15: After the GDS file is released , |
| blockages are created where the tool is | | | | perform the LAPO check so that the database |
| prevented from placing the cells, then the | | | | released to the fab is correct. |
| physical placement of the cells is performed | | | | |
| based on the timing/area requirements.The | | | | Step 16: Perform the Package wire-bonding, |
| power-grid is built to meet the | | | | which connects the chip to the Package. |