| Step 1: Prepare an Requirement Specification | | | | first the Global routing and Detailed routing, meeting |
| Step 2: Create an Micro-Architecture Document. | | | | the DRC(Design Rule Check) requirement as per the |
| Step 3: RTL Design & Development of IP's | | | | fabrication requirement. |
| Step 4: Functional verification all the IP's/Check | | | | Step 11: After performing Routing then the routed |
| whether the RTL is free from Linting Errors/Analyze | | | | Verilog netlist, standard-cells LEF/DEF file is taken to |
| whether the RTL is Synthesis friendly. | | | | the Extraction tool (to extract the parasitics(RLC) |
| Step 4a: Perform Cycle-based verification(Functional) | | | | values of the chip in the SPEF format(Standard |
| to verify the protocol behaviour of the RTL | | | | parasitics Exchange Format), and the SPEF file is |
| Step 4b: Perform Property Checking , to verify the | | | | generated. |
| RTL implementation and the specification | | | | Step 12: Check whether the Design is meeting the |
| understanding is matching. | | | | requirements (Functional/Timing/Area/Power/DFT |
| Step 5: Prepare the Design Constraints file (clock | | | | DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and |
| definitions(frequency/uncertainity/jitter),I/O delay | | | | Routing step. |
| definitions, Output pad load definition, Design False | | | | Step 12a: Perform the Routed Netlist-level Power |
| Multicycle-paths) to perform Synthesis, usually called | | | | Analysis, to know whether the design has met the |
| as an SDC synopsys_constraints, specific to | | | | power targets. |
| synopsys synthesis Tool (design-compiler) | | | | Step 12b: Perform Gate-level Simulation with the |
| Step 6: To Perform Synthesis for the IP, the inputs | | | | routed Netlist to check whether the design is |
| to the tool are (library file(for which synthesis needs | | | | meeting the functional requirement . |
| to be targeted for, which has the functional/timing | | | | Step 12c: Perform Formal-verification between RTL |
| information available for the standard-cell library and | | | | vs routed Netlist to confirm that the place & route |
| the wire-load models for the wires based on the | | | | Tool has not altered the functionality. |
| fanout length of the connectivity), RTL files and the | | | | Step 12d: Perform STA(Static Timing Analysis) with |
| Design Constraint files, So that the Synthesis tool can | | | | the SPEF file and routed netlist file, to check whether |
| perform the synthesis of the RTL files and map and | | | | the Design is meeting the timing-requirements. |
| optimize to meet the design-constraints requirements. | | | | Step 12e: Perform Scan-Tracing , in the DFT tool, to |
| After performing synthesis, as a part of the | | | | check whether the scan-chain is built based on the |
| synthesis flow, need to build scan-chain connectivity | | | | DFT requirement, Peform the Fault-coverage with |
| based on the DFT(Design for Test) requirement, the | | | | the DFT tool and Generate the ATPG test-vectors. |
| synthesis tool (Test-compiler), builds the scan-chain. | | | | Step 12f: Convert the ATPG test-vector to a tester |
| 7: Check whether the Design is meeting the | | | | understandable format(WGL) |
| requirements (Functional/Timing/Area/Power/DFT) | | | | Step 12g: Perform DRC(Design Rule Check) |
| after synthesis. | | | | verfication called as Physical-verification, to confirm |
| Step 7a: Perform the Netlist-level Power Analysis, to | | | | that the design is meeting the Fabrication |
| know whether the design is meeting the power | | | | requirements. |
| targets. | | | | Step 12h: Perform LVS(layout vs Spice) check, a part |
| Step 7b: Perform Gate-level Simulation with the | | | | of the verification which takes a routed netlist |
| Synthesized Netlist to check whether the design is | | | | converts to spice (call it SPICE-R) and convert the |
| meeting the functional requirements. | | | | Synthesized netlist(call it SPICE-S) and compare that |
| Step 7c: Perform Formal-verification between RTL vs | | | | the two are matching. |
| Synthesized Netlist to confirm that the synthesis | | | | Step 12i : Perform the ERC(Electrical Rule Checking) |
| Tool has not altered the functionality. | | | | check, to know that the design is meeting the ERC |
| Step 7d: Perform STA(Static Timing Analysis) with | | | | requirement. |
| the SDF(Standard Delay Format) file and synthesized | | | | Step 12j: Perform the ESD Check, so that the proper |
| netlist file, to check whether the Design is meeting | | | | back-to-back diodes are placed and proper guarding is |
| the timing-requirements. | | | | there in case if we have both analog and digital |
| Step 7e: Perform Scan-Tracing , in the DFT tool, to | | | | portions in our Chip. We have seperate Power and |
| check whether the scan-chain is built based on the | | | | Grounds for both Digital and Analog Portions, to |
| DFT requirement. | | | | reduce the Substrate-noise. |
| Step 8: Once the synthesis is performed the | | | | Step 12k: Perform seperate STA(Static Timing |
| synthesized netlist file(VHDL/Verilog format) and the | | | | Analysis) , to verify that the Signal-integrity of our |
| SDC (constraints file) is passed as input files to the | | | | Chip. To perform this to the STA tool, the routed |
| Placement and Routing Tool to perform the back-end | | | | netlist and SPEF file(parasitics including coupling |
| Actitivities. | | | | capacitances values), are fed to the tool. This check |
| Step 9: The next step is the Floor-planning, which | | | | is important as the signal-integrity effect can cause |
| means placing the IP's based on the | | | | cross-talk delay and cross-talk noise effects, and |
| connectivity,placing the memories, Create the | | | | hinder in the functionality/timing aspects of the |
| Pad-ring, placing the Pads(Signal/power | | | | design. |
| transfer-cells(to switch voltage domains/Corner | | | | Step 12l: Perform IR Drop analysis, that the |
| pads(proper accessibility for Package routing), | | | | Power-grid is so robust enough to with-stand the |
| meeting the SSN requirements(Simultaneous | | | | static and dynamic power-drops with in the design |
| Switching Noise) that when the high-speed bus is | | | | and the IR-drop is with-in the target limits. |
| switching that it doesn't create any noise related | | | | Step 13: Once the routed design is verified for the |
| acitivities, creating an optimised floorplan, where the | | | | design constraints, then now the next step is |
| design meets the utilization targets of the chip. | | | | chip-finishing activities (like metal-slotting, placing |
| Step 9a : Release the floor-planned information to the | | | | de-coupling caps). |
| package team, to perform the package feasibility | | | | Step 14: Now the Chip Design is ready to go to the |
| analysis for the pad-ring . | | | | Fabrication unit, release files which the fab can |
| Step 9b: To the placement tool, rows are cut, | | | | understand, GDS file. |
| blockages are created where the tool is prevented | | | | Step 15: After the GDS file is released , perform the |
| from placing the cells, then the physical placement of | | | | LAPO check so that the database released to the |
| the cells is performed based on the timing/area | | | | fab is correct. |
| requirements.The power-grid is built to meet the | | | | Step 16: Perform the Package wire-bonding, which |
| power-target's of the Chip . | | | | connects the chip to the Package. |
| Step 10: The next step is to perform the Routing., at | | | | |